1. Field of Invention
This invention relates in general to manufacturing method of a dielectric layer for dynamic random-access-memory (DRAM) capacitors, and more particularly to the manufacturing method of a dielectric layer that can improve a capability of storing charges in capacitors of DRAM.
2. Description of Related Art
DRAM is a kind of volatile memory whose digital signals are stored according to the charging state of the respective capacitors in each of the memory cells. Each memory cell is included of a MOS transistor and a capacitor. The capacitor is the important part of the memory cell. The more charges stored in the capacitor, the less effect produced by reading data stored in the cell, and the less times for refreshing the memory cell. The conventional methods for increasing the charges stored in the capacitor of the memory cell are: (1) increasing the surface of the capacitor, it increases charges stored in the whole capacitor, but it results in reducing integration of the DRAM devices; (2) using a proper materials of the dielectric layer for increasing a dielectric constant thereof, it makes charges stored in an unit-area of the capacitor increasing; (3) reducing the thickness of the dielectric layer, but it is restricted to a minimum thickness owing to features of the dielectric layer and the technique of manufacturing.
The conventional manufacturing method of a dielectric layer of the DRAM capacitor is forming an ONO (Oxide-nitride-oxide) layer, that is, depositing dielectric materials onto a lower electrode layer of the capacitor in the DRAM, implementing a process of oxidation, and then depositing an upper electrode onto the dielectric layer. After that, a structure of the capacitor in the DRAM will be implemented. Referring to FIG. 1A to FIG. 1C, it shows a conventional manufacturing method of a DRAM capacitor, At first, referring to FIG. 1A, parts of a MOS transistor and a substrate in a DRAM memory cell are skipped and are not shown. The lower electrode 14 of the capacitor is made up of, for example, polysilicon. There is a conducting line 10 below the lower electrode 14 for connecting source/drain regions (not shown) of the MOS transistor. The isolating layer 12 is, for example, an inter poly dielectric and is for isolating from the other memory cells.
Next, referring to FIG. 1B, when the lower electrode 14 is already formed, there is a native oxide layer in sequence formed over a surface of the lower electrode 14 with a circumstance filled with oxygen. The reaction can be performed at room temperature, and therefore the native oxide layer is formed as a very thin layer which is the first layer of three layers constituting a structure of the ONO layer. But the native oxide layer is not suitable for being a dielectric layer of the capacitor owing to its small dielectric constant. Therefore, it is usually peeled by an acidic reaction process, for example, with hydrofluoric acid. Then a nitride layer 16, for example, a silicon nitride, is formed as a second layer of the ONO structure. The nitride layer 16 improves features of the dielectric layer of the capacitor owing to its high dielectric constant.
Then, referring to FIG. 1C, because the nitride layer 16 is formed with a process of deposition. There are some pinholes formed in the surface of the nitride layer 16 after depositing. It results in a situation that a leakage current is found after depositing conductive materials in following steps onto the nitride layer 16 because these pinholes in the nitride layer 16 are filled with these conductive materials. Avoiding this situation happens, a very thin silicon dioxide layer 18 is usually formed by an oxidation method onto the nitride layer 16 in order to fill the pinholes before these conductive materials are deposited. The silicon dioxide layer 18 is the third layer of the ONO structure. Next, a upper electrode 24 is deposited onto the silicon dioxide layer 18 and then a method of manufacturing the capacitor is performed.
The convention method for the nitride layer of the ONO structure is formed by depositing. It will not be possible to form a very thin nitride layer. Furthermore, the silicon dioxide layer above the nitride layer will cause the dielectric constant of the dielectric layer reduced because of a low dielectric constant of the silicon dioxide layer. These defects will effect features of the DRAM.